The connection can be the bottleneck
Making a transistor thinner is useful only if electricity can enter and leave it effectively. A KAIST-led team has addressed that contact problem with tin diselenide, or SnSe2. Its approach works with both n-type and p-type ultrathin semiconductor channels, potentially simplifying a difficult part of future chip design.
The timing needs care: KAIST's announcement describes a September 16 release, distributed through EurekAlert on September 15. The Advanced Materials paper appeared online on August 12. This is newly highlighted research, not the launch of a commercial processor.
The practical question is whether one well-behaved interface can reduce the number of compromises needed to build a useful circuit. The attraction is understandable; the distance from a promising device to a manufacturable computing platform remains substantial.
Sources: KAIST: single-material charge-injection announcement; Cho and colleagues: A Universal van der Waals Tunneling Injector for Monolayer CMOS
One contact material, two complementary devices
The researchers use the same injector with monolayer tungsten diselenide, WSe2, for p-type devices and molybdenum disulfide, MoS2, for n-type devices. The energy alignment differs at the two interfaces, enabling different tunnelling mechanisms. The claim is a shared injection platform—not that every transistor component becomes identical.
In plain language, improving the route into a device can matter as much as improving the device's active material. An illustrative comparison is a well-designed road served by an inadequate junction: widening the road alone may not increase the useful flow. This is an analogy, not a literal model of quantum transport.
Imec's technical roadmap explains the broader difficulty. Conventional silicon-contact and doping techniques do not transfer straightforwardly to atomically thin materials. The most promising materials for n-type and p-type devices are also different. A common contact strategy would therefore address a genuine integration problem rather than merely create another thin material.
Sources: Cho and colleagues: A Universal van der Waals Tunneling Injector for Monolayer CMOS; Imec: introducing 2D devices in the logic-scaling roadmap
Why '1,000 times' does not mean a 1,000-times faster computer
The paper reports more than a thousandfold improvement in p-type drive current against its conventional metal-electrode comparison. For n-type devices, it reports an on/off current ratio above one billion. The researchers also demonstrate a CMOS inverter, with peak voltage gain around 340 at a 2-volt supply.
These quantities describe different things. Drive current concerns conduction in a device; an on/off ratio compares conducting and nonconducting states; inverter gain describes how an output responds to an input. None is a measurement of application speed, battery life or the electricity consumed by an AI data centre.
Our interpretation is that a striking relative improvement is most useful when the baseline is visible. Fixing a particularly poor interface can produce a very large ratio without implying a comparable advantage over a leading commercial processor. Readers should resist converting a component measurement into a whole-system performance claim.
Sources: Cho and colleagues: A Universal van der Waals Tunneling Injector for Monolayer CMOS
The other challenge: repeating it across a wafer
A separate June 2026 collaboration between imec, ASML and TSMC provides relevant industrial context. That team described n-type and p-type 2D transistors integrated on 300-millimetre wafers, with 50-nanometre contacted poly pitch. It reported 94% operational transistors under its stated current-ratio criterion. This is not a result from the KAIST injector study.
The comparison is useful because the projects address different questions. A contact experiment asks whether a material combination can work well. A wafer-integration programme asks whether compatible devices can be fabricated repeatedly at relevant dimensions. Neither milestone, by itself, establishes that a complex processor is ready to ship.
Imec's roadmap also identifies reliability and device-to-device variability as remaining concerns. For a manufacturer, the distribution matters alongside the best result. Our illustrative factory test would therefore ask how many acceptable devices emerge from the entire process, not whether one carefully selected transistor produces an impressive graph.
Sources: Imec: introducing 2D devices in the logic-scaling roadmap; Imec, ASML and TSMC: separate 300mm integration research, June 15
A possible efficiency gain—not an energy forecast
KAIST describes opportunities for future vertically integrated, low-power electronics, while identifying further work in direct growth, large-area fabrication and integration. That is a development direction. It should not be read as a production timetable or a promise that current AI infrastructure will soon consume a particular amount less electricity.
Our economic reading is that simpler integration could be valuable if it survives manufacturing. Fewer incompatible process requirements might eventually reduce development effort or enable useful device arrangements. But new materials also bring qualification, equipment and supply-chain costs. A promising contact can shift the engineering problem without eliminating the bill.
For users, the eventual question is energy per useful task at an acceptable price and lifetime. A future chip would still contain memory, interconnects and other components. It is therefore possible for a better transistor to be important without delivering the same percentage improvement in a complete computer.
Sources: KAIST: single-material charge-injection announcement; Imec: introducing 2D devices in the logic-scaling roadmap
Scientific perspective: put the benchmark in its proper box
Lumacta's evidence-based assessment is that the advance should be judged as contact and circuit research, not as a finished AI-chip breakthrough. This is our editorial interpretation of the linked evidence, not independent peer review, laboratory replication or investment advice.
We would look next for comparable results across many devices, transparent fabrication conditions, stability over time and measurements under application-relevant operating conditions. Comparisons should use credible baselines and disclose trade-offs rather than selecting only the largest improvement. These are proposed evaluation criteria, not additional outcomes already established here.
The broader lesson is that progress in semiconductors often comes from making interfaces and processes less troublesome. That can be less visually dramatic than a new processor launch, yet more consequential over the long term. The strongest conclusion today is a narrower, useful one: a difficult electrical connection has gained a promising research approach; a commercial computing advantage still has to be earned.
Sources: Cho and colleagues: A Universal van der Waals Tunneling Injector for Monolayer CMOS; Imec: introducing 2D devices in the logic-scaling roadmap; Imec, ASML and TSMC: separate 300mm integration research, June 15
Sources & Methods
Checked September 16, 2026. Read the original Advanced Materials paper and KAIST's distributed announcement; used imec documentation as separate industrial context, not an endorsement or replication of the injector. Component measurements are not processor benchmarks. Commercial implications and the scientific perspective are original analysis.
- KAIST: single-material charge-injection announcement — University-authored research announcement
- Cho and colleagues: A Universal van der Waals Tunneling Injector for Monolayer CMOS — Original peer-reviewed research, August 12, 2026
- Imec: introducing 2D devices in the logic-scaling roadmap — Research institute's technical background
- Imec, ASML and TSMC: separate 300mm integration research, June 15 — Independent research-programme context